1. Field of the Invention
The present invention relates to a level transforming circuit serving as an interface of a digital circuit, wherein the level transforming circuit operates with different electricity source voltages.
2. Description of Related Art
The finer the structure of a MOS transistor becomes, the weaker the strength of a gate oxide film becomes. For example, a MOS transistor produced in a fine process of an extent of 0.35 μm is able to operate at an electricity source voltage of an extent of 3.3V. Further, a MOS transistor produced in a latest fine process of an extent of 0.18 μm is able to operate at an electricity source voltage of an extent of 1.8V. In the conventional art, when it is necessary to make an interface between a circuit of 0.18 μm fine process and a circuit of 0.35 μm fine process, a level transforming circuit in the interface required both MOS transistors of 1.8V and 3.3V.
(First Prior Art)
FIG. 10 is a circuit diagram showing a structure of a level transforming circuit of a first prior art disclosed in Japanese patent publication No. 4-150411. This level transforming circuit comprises, as shown in FIG. 10, a latch circuit 200, which operates with a high voltage electricity source VDD (3.3V). NMOS 211 and 212 are connected between node N11, N12 of this latch circuit 200 and the ground. A signal IN from a circuit which operates with a low voltage electricity source VCC (1.8) is impressed to the gate of NMOS 211. On the other hand, an inverse signal of the signal IN driven by an inverter 213, which operates with a low voltage electricity source VCC (1.8) as well, is impressed to the gate of NMOS 212. Provided that node N11, N12 of latch circuit 200 is respectively 3.3V, 0V; if the signal IN becomes 3.3V, NMOS 211 turns on and NMOS 212 turns off. As a result, node N11 becomes 0V and node N12 becomes 3.3V. Then, the input signal IN is transformed from 1.8V to 3.3V, and the signal latched in the latch circuit 200 is obtained from the node N12.
(Second Prior Art)
FIG. 11 is a circuit diagram showing a structure of a level transforming circuit of a second prior art disclosed in Japanese patent publication No. 6-216752. This level transforming circuit comprises MOS transistors having a dielectric strength of a gate oxide film which is lower than a high voltage (5V), so as to transform a level from a low voltage electricity source system to a high voltage electricity source system. As shown in FIG. 11, this level transforming circuit comprises a level transforming section comprising MOS transistors 300 to 313, and an output section comprising NOS transistors 314 to 317. The level transforming section has input the signal IN of a low voltage (VCC:3V) electricity source system, so as to output a signal for a transforming level to node N21, N22. The output section has input a control signal from the level transforming section mentioned above, so as to output an output signal OUT1 having an amplitude of 0V to 5V as a high voltage (VDD:5V) electricity source system, an output signal OUT2 having an amplitude of an intermediate electric potential to 5V, and an output signal OUT3 having an amplitude of 0V to an intermediate electric potential.
Here, described is an occasion when an output enable signal OE and its inverse signal OEB are inputted with H level and L level respectively. If input signal IN becomes L level; PMOS 306, 307 turns on and NMOS 305, 312 turns off. As a result, node N23, N24 becomes H level, and NMOS 304 turns on. Then, source electric potential of NMOS 302 decreases, and a route of current comprised of NMOS 302, PMOS 301 is taken. On the other hand, node N25 is pulled down, and PMOS 308 turns on. When PMOS 308 turns on, node N21 becomes H level, and PMOS 309 turns on. Then, source electric potential of NMOS 310 is pulled up to the high voltage VDD. Moreover, when node N24 becomes H level, NMOS 311 is on, because the output enable signal EB is H level. Then, node N22 becomes H level, and output signal OUT3 becomes 0V. When node N21 becomes H level, PMOS 314 turns off, and output signal OUT2 becomes an intermediate electric potential. Output signal OUT1 becomes 0V, as NMOS 316 turns on, because output signal OUT3 is 0V.
On the other hand, if input signal IN becomes H level; NMOS 305, 312.turns on and PMOS 306, 307 turns off. Then, nodes N22, N23 are pulled down, and NMOS 317 turns off. Since NMOS 311 is on, node N24 is pulled down, and a route of current comprised of PMOS 309, NMOS 310 is taken. PMOS 314 turns on when node N21 is pulled down, and PMOS 300 turns on, so as to pull up node N25. Output signal OUT1 becomes 5V, output signal OUT2 becomes 5V, and output signal OUT3 becomes an intermediate electric potential.
(Third Prior Art)
FIG. 12 is a circuit diagram showing a structure of a level transforming circuit of a third prior art disclosed in Japanese patent No. 3258229. This level transforming circuit comprises MOS transistors with a dielectric strength of a gate oxide film which is lower than a high voltage (5V), so as to transform a level from a low voltage electricity source system to a high voltage electricity source system, similar to the second prior art. As shown in FIG. 12, this level transforming circuit comprises CMOS circuit 10, intermediate circuit 30, 40, and CMOS circuit 20.
CMOS circuit 10 comprises PMOS 11, 12 and NMOS 13, 14. PMOS 11, 12 are connected in series between the high voltage electricity source (VDD: 5V) and output node N1. NMOS 13, 14 are connected in series between the node N1 and the ground. The gate of PMOS 11 for pulling up is connected with node N4. On the other hand, the gate of NMOS 14 for pulling down is inputted with a signal IN which amplitude is between a low voltage (VCC: 3V) and the ground. On the other hand, each gate of PMOS 12 and NMOS 13 is impressed with the low voltage in common.
The intermediate circuit 30 comprises PMOS 31, 32. PMOS 31 is connected between the high voltage electricity source VDD and output node N3, and its gate is connected with node N4. On the other hand, PMOS 32 is connected between node N3 and the low voltage electricity source VCC, and its gate is connected with output node N1 of CMOS circuit 10.
The intermediate circuit 40 comprises PMOS 41, 42. PMOS 41 is connected between the high voltage electricity source VDD and output node N4,and its gate is connected with node N3. On the other hand, PMOS 32 is connected between node N4 and the low voltage electricity source VCC, and its gate is impressed with output signal OUT1.
CMOS circuit 20 comprises PMOS 21, 22 and NMOS 23, 24. PMOS 21, 22 are connected in series between the high voltage electricity source VDD and output node N2. NMOS 23, 24 are connected in series between the output node N2 and the ground. The gate of PMOS 21 for pulling up is connected with node N3. On the other hand, the gate of NMOS 24 for pulling down is inputted with an inverse signal of the input signal IN. Each gate of PMOS 22 and NMOS 23 is impressed with the low voltage in common.
Hereafter, the operation of this circuit is described.
When the input signal is the low voltage level VCC, NMOS 14 turns on. Thus, PMOS 32 turns on. As a result, PMOS 41, 21 turn on. On the other hand, NMOS 24 turns off by the inverse signal of the input signal. Thus, PMOS 42 turns off. Therefore, an output signal of the high voltage level VDD is output. In this state, direct current does not pass through the circuit because PMOS 11, 31, 42 and NMOS 24 are in an off state.
On the other hand, when the input signal changed from the low voltage level VCC to the ground level (0V level), NMOS 24 turns on. Thus, PMOS 42 turns on. As a result, PMOS 11, 31 turn on, and NMOS 14 turns off by the inverse signal of the input signal. Thus, PMOS 32 turns off. Therefore, an output signal of the ground level (0V level) is output. In this state, direct current does not pass through the circuit because PMOS 21, 41, 32 and NMOS 14 are in an off state.
However, the level transforming circuit of the conventional art have problems.
For example, as for the first prior art (FIG. 10), transistors having a gate oxide film strength higher than the voltage level VDD of high voltage electric source are used as some of the transistors, these transistors being each of two inverters comprising latch circuit 200 and NMOS 211, 212. Therefore, the gate oxide films of these transistors must be thick and their gate length must be long. In addition, in order to make MOS transistors capable of enduring high voltage, some portions of an integrated circuit on a semiconductor chip must be treated specially. Thus, there is a problem that a manufacturing process becomes complicated.
On the other hand, as for the second prior art (FIG. 11), a level transforming circuit is able to comprise only transistors having gate oxide film strength lower than the high voltage level VDD. However, the second prior art limits an amplitude of a gate voltage (node N21) of PMOS 314, by using the effect of turning off PMOS 309; so as to restrain the gate voltage under the strength of a gate oxide film less than the high voltage level VDD. Meanwhile, the gate of PMOS 309 is impressed with an electric potential VB. Therefore, the electric potential of the gate of PMOS 309 does not decrease less than VB+Vth, even if a logical value of node N21 is L level. Here, Vth is a threshold voltage of PMOS.
While PMOS 309 is turning off, the electric potential of node N1 gradually comes to VB+Vth. The level transforming circuit of the second prior art uses this motion, and therefore, could not operate rapidly.
Moreover, the gate voltage of PMOS 314 (electric potential of node N21) becomes VDD−(VB+Vth). Thus, if (VB+Vth) is higher than 0V, the gate voltage becomes low. Therefore, there is another problem that the ability to bear a load of the output section decreases. Moreover, the output signal OUT1 rises to 5V from 0V, when NMOS 317 turns off and PMOS 314 turns on. In this occasion, the source potential of PMOS 315 is pulled up rapidly. Therefore, the voltage Vgs between the gate and source of PMOS 315 becomes a voltage such that the current flowing in PMOS 315 is equal to the current flowing in PMOS 314. Thus, between the source and drain of PMOS 314, a voltage of VCC+Vgs is impressed. Similarly, output signal OUT1 drops to 0V from 5V, when PMOS 314 turns off and NMOS 317 turns on. In this occasion, the source potential of NMOS 316 is pulled down rapidly. Therefore, the voltage Vgs between gate and source of NMOS 316 becomes a voltage such that the current flowing in NMOS 316 is equal to the current flowing in NMOS 317. So, between the source and drain of NMOS 316, a voltage of VCC+Vgs is impressed. Therefore, a voltage exceeding the voltage preferred in a low voltage electricity source system is transiently impressed between the source and drain. Thus, an ability of the device is deteriorated by a hot carrier. As a result, a problem was caused in that the reliability of the device deteriorates.
Moreover, as for the third prior art (FIG. 12), a level transforming circuit is able to comprise only transistors having a gate oxide film strength lower than the high voltage level VDD. However, in the third prior art, as for CMOS circuit 10, a turning on resistance of PMOS 11, 12 is set higher than a turning on resistance of NMOS 13, 14. As for CMOS circuit 20, a turning on resistance of PMOS 21, 22 is set higher than a turning on resistance of NMOS 23, 24. As for intermediate circuit 30, a turning on resistance of PMOS 31 is set higher than a turning on resistance of PMOS 32. As for intermediate circuit 40, a turning on resistance of PMOS 41 is set higher than a turning on resistance of PMOS 42. Therefore, the third prior art has the following problem.
When input signal IN becomes the low voltage level VCC from the ground level, the electric potential of node N1 rises rapidly because the turning on resistance of NMOS 13, 14 is lower than the turning on resistance of PMOS 11, 12, and the voltage between source and drain of PMOS 12 becomes VCC+Vgs. Here, Vgs is the gate source voltage of PMOS 12, which flows current in PMOS 12 the same as the current flowing in PMOS 11. Thus, the voltage between the source and drain transiently becomes higher than VCC. Similarly, the voltage between the gate and source of PMOS 32 becomes VCC+Vgs. Here, Vgs is the gate source voltage of PMOS 32, which flows current in PMOS 32 the same as the current flowing in PMOS 31. Thus, the voltage between the gate and source transiently becomes higher than VCC. Therefore, voltage exceeding the voltage preferred in a low voltage electricity source system is transiently impressed between the source and drain. Moreover, voltage exceeding the voltage preferred in a low voltage electricity source system is transiently impressed between the gate and source. Thus, the ability of the device is deteriorated by a hot carrier. As a result, a problem was caused in that the reliability of the device deteriorates.
Moreover, with dropping of output node N3, output node N2 is pulled up by the turning on current of PMOS 21 flowing through PMOS 22. There is an occasion when a buffer to drive a succeeding output stage is provided to the level transforming circuit of FIG. 12. This buffer comprises two PMOS's (first PMOS and second PMOS) which are connected in series between the high voltage electricity source VDD and the low voltage electricity source VCC. The source of the first PMOS is connected with the high voltage electricity source VDD. The drain of the second PMOS is connected with the low voltage electricity source VCC. The gate of the first PMOS is connected with output node N3. The gate of the second PMOS is connected with output node N2. In this occasion, the first PMOS comes into an on state, while the second PMOS is still in an on state. Therefore, passing current flows from the high voltage electricity source VDD to the low voltage electricity source VCC. As a result, a problem is caused of increasing electricity consumption in vain.
Moreover, as described in Japanese patent 3258229, in the occasion when the output stage of the semiconductor integrated circuit is driven, each transistor of the output stage usually has a gate width of several hundred μm. Thus, as for a gate width of each transistor of a buffer driving this transistor of the output stage, if it is narrower than several hundred μm, current flowing through the output stage decreases. As a result, a problem is caused of deteriorating high mobility of the output stage.
The present invention is aimed at providing a novel and improved level transforming circuit, which is able to operate fast and to restrain drivability drop, so as to solve the problems contained in the level transforming circuit of the prior art mentioned above.